This invention relates to a Carry Increment Adder (CIA) which applies to accumulators used in a Digital Signal Processor (DSP) or microprocessor. More particularly, this invention relates to a CIA using a clock phase in which the CIA is fast and is achieved by using a much smaller chip area than a general fast adder structure.
Generally, adders are used in digital systems such as a DSP or microprocessor. Additionally, adders are important in determining performance of a computer or a computer program.
Accordingly, adders have been structurally researched due to their long term importance. A Ripple Carry Adder (RCA), a simple adder structure, is well known in the art. The RCA has one of the lowest speeds. This is due, in part to the bit width of addend which increases due to the decrement of speed resulting from the delay of the carry ripple. This causes the increments in linear delay to occur.
To overcome the problems of RCAs, many adder structures such as Carry Lookahead Adder (CLA), Carry Skip Adder (CSA), and Carry Select Adder (CSA) have been devised and used in practice. However, most adders have trade-off characteristics of speed and chip area according to their structures. To illustrate, most high speed adders generally require a large chip area. In the case of a RCA, an adder that has the lowest speed, the least chip area is required. Accordingly, one has to select the proper adder structures in the systems which need them by balancing the desired speed against the amount of chip area needed.
FIG. 1 shows a block view of an 8-bit CIA, divided by first and second modules. Each module has the desired bits to record the partial sum and partial carry. The first module comprises a lower 4-bit RCA (11) which outputs lower 4-bit sum values (S3-S0) of a and b inputs (each has 8 bits) and a carry value which occurs during the summation. The second module comprises a higher 4-bit RCA (12) which outputs higher 4 bit sum values (In3 through In0) of a and b inputs, and conditional increment (13) which output sum values (S7 through S4) of output value (In3-In0) of the higher 4-bit RCA (12) and carry value (C1).
In the operation of the CIA, at first, a and b inputs of 8 bits are added through two 4-bit RCAs (11, 12). That is, each of the higher 4 bits and lower 4 bits of a and b inputs are added in parallel. At this moment, carry input (C1) is assumed to be 0. After the higher 4 bits and lower 4 bits of a and b inputs are added simultaneously, the conditional increment (13) increases the values (In3-In0) calculated in the higher 4-bit RCA (12) by 1 when the carry occurs in the lower 4-bit RCA (11). The values calculated in the higher 4-bit RCA (12) are output when no carry occurs.
However, the area of the conditional increment should be considered in the carry increment adder, and it becomes a serious problem especially when this technology applies to the semiconductor devices requiring large scale integration.